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Espressif Systems /ESP32-P4 /HP_SYS_CLKRST /CPU_CLK_STATUS0

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Interpret as CPU_CLK_STATUS0

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31282724232019161512118743000000000000000000000000000000000000000000 (REG_ASIC_OR_FPGA)REG_ASIC_OR_FPGA0 (REG_CPU_DIV_EFFECT)REG_CPU_DIV_EFFECT0 (REG_CPU_SRC_IS_CPLL)REG_CPU_SRC_IS_CPLL0REG_CPU_DIV_NUM_CUR0REG_CPU_DIV_NUMERATOR_CUR0REG_CPU_DIV_DENOMINATOR_CUR

Description

CPU Clock Status

Fields

REG_ASIC_OR_FPGA

0: ASIC mode, 1: FPGA mode
REG_CPU_DIV_EFFECT

0: Divider bypass, 1: Divider takes effect
REG_CPU_SRC_IS_CPLL

0: CPU source isn’t cpll_400m, 1: CPU Source is cll_400m
REG_CPU_DIV_NUM_CUR

cpu current div number
REG_CPU_DIV_NUMERATOR_CUR

cpu current div numerator
REG_CPU_DIV_DENOMINATOR_CUR

cpu current div denominator

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data